feat(cortex-m3): peripheral IRQ pipeline — C2/C1/C3#4
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feat(cortex-m3): peripheral IRQ pipeline — C2/C1/C3#4Charliechen114514 wants to merge 3 commits into
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raise_irq was a no-op — the entire peripheral→NVIC IRQ channel was never connected (SysTick bypassed it via sys_tick_irq). Implement it as nvic_->set_pending(irq); this is the shared entry for all MMIO IRQs (TIM/USART/EXTI). Stm32f1Timer gains set_irq_callback (SysTick pattern); tick() raises on UIF 0→1 edge when DIER.UIE is set. SoC wires TIM2 (kTim2Irqn=28). Add unit tests (edge/UIE semantics) and TimerUifRoundtrip E2E (coordinator Apb1 tick → handler entry → BX LR return). ctest 289/289.
Add Stm32f1Exti (IMR/EMR/RTSR/FTSR/SWIER/PR @ 0x40010400). GPIO edges → AFIO EXTICR routing (new exti_line_port getter) → IMR+RTSR/FTSR match → pending + raise NVIC (line→IRQ: 0-4=6-10, 5-9=23, 10-15=40). Reuses the raise_irq channel from C2 (EXTI is its second consumer). GPIO simulate_input now emits edge_signal so external input edges feed EXTI. SoC wires gpioa/b/c edge_signal → EXTI → raise_irq. Tests: 6 unit (registers/PR/routing/mask/edge-select) + ExtiGpioEdgeRoundtrip E2E. ctest 296/296.
USART gains inject_rx(byte): single-slot RX buffer + SR.RXNE, DR read returns the byte and clears RXNE (read=RX/write=TX shared). RXNEIE (CR1 bit5) + RXNE → raise USART1 (IRQ37) via the raise_irq channel — its third consumer (TIM/EXTI/USART). TXEIE skipped (instant TX keeps TXE high → would loop-raise; firmware polling TXE still works). Tests: 4 unit (RXNE/DR/RXNEIE enabled+disabled) + UsartRxRoundtrip E2E (inject_rx → handler reads DR via r4, which survives exception return unlike auto-stacked r0-r3). ctest 301/301.
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外设中断端到端(06 第二波 C2/C1/C3)
打通外设 → NVIC → handler 的完整中断通道,三个外设(TIM/EXTI/USART)端到端跑通,验证第一波 A 抢占模型在真实外设上成立。
C2 — raise_irq 公共通道 + Timer UIF→IRQ (
84c73e6)raise_irq原为空壳 no-op → 实现为nvic_->set_pending(irq)。这是所有 MMIO IRQ 的公共入口(SysTick 之前靠独立sys_tick_irq绕过)。C1 — EXTI 外部中断 + AFIO EXTICR (
857fb0e)Stm32f1Exti(IMR/RTSR/FTSR/SWIER/PR)+ AFIOexti_line_port路由(EXTICR 终于有消费者)。simulate_input补 edge emit(外部输入边沿喂 EXTI)。C3 — USART RX 注入 + RXNEIE (
0364f16)inject_rx单字节缓冲 + RXNE;DR read 返回字节 + 清 RXNE(读=RX/写=TX 共享)。验证
细节
MICRO_FORGE_SOURCES显式set()列表(非 DIRECTIVES 说的 GLOB);ARM 异常自动压栈 r0-r3(handler 读结果用 r4+)。🤖 Generated with Claude Code