GF180MCU: power-pin + wired-filler shortcuts for real post-P&R netlists

[robtaylor]

Summary

Phase 6 brought GF180MCU support up to "synthesized-core-only". Trying jacquard sim against a real gf180mcu-project-template post-P&R chip_top netlist surfaces two gaps that the synthetic timing_test fixtures didn't exercise:

1. Power pins are inout in Verilog models, missing from the pin table. Cells like gf180mcu_fd_sc_mcu7t5v0__antenna declare inout VDD, VSS, VNW, VPW;. build.rs::generate_gf180mcu_pin_table only parses input / output declarations, so the generated GF180MCU_PIN_TABLE has no entries for power pins. Real post-P&R netlists wire them (e.g. .VDD(VDD), .VNW(VDD), .VPW(VSS), .VSS(VSS)), and NetlistDB panics on the first lookup.

2. Filler / corner cells get wired power pins. Upstream's is_filler_cell whitelist already classifies cor / fill* / dvdd / dvss etc., but the assumption was these instantiate with empty port lists (). The gf180mcu-project-template LibreLane flow wires all four power pins on every filler — gf180mcu_fd_io__cor ships with .DVDD .DVSS .VDD .VSS. With no pin-table entry these also panicked.

Fix

Two short-circuits ahead of the per-cell pin-table lookup in GF180MCULeafPins::direction_of:

• Power-pin shortcut: any pin named VDD / VSS / VNW / VPW / VPB / VNB / VPWR / VGND / DVDD / DVSS / AVDD / AVSS resolves to Direction::I. The Direction enum has no Inout variant — power semantics (driven from supply, never driven by the cell) match "constant external driver" / input.

• Wired-filler shortcut: any pin on a cell classified by is_filler_cell falls through to Direction::I. Fillers carry no logic, so power, ground, and any wired signal pin are all sim-irrelevant from the AIG's perspective.

DVDD/DVSS/AVDD/AVSS are wafer.space-PDK power-pad naming.

Tests

Three new unit tests in gf180mcu::tests (all passing — cargo test --lib gf180mcu is 59/59 with this change, up from 56):

• pin_provider_returns_directions_for_power_and_ground_pins — exercises all 12 power-pin names against an antenna cell.
• pin_provider_handles_wired_filler_and_corner_cells — covers cor / fill10 / filltie / endcap / dvdd / dvss with realistic pin lists.
• netlist_db_parses_wired_chip_top_pad_ring — integration fixture mirroring a real gf180mcu-project-template post-P&R chip_top with wired antenna, corner, filler, endcap, and ws_io power pads.

Existing netlist_db_parses_chip_top_pad_ring (empty-port-list version) continues to pass — both shapes are now covered.

What this doesn't fix

gf180mcu_ocd_ip_sram__sram1024x8m8wm1 (third-party RTimothyEdwards SRAM IP, vendored separately). It's not in any upstream pin table and needs richer modelling than fillers (real ports A/D/Q/WE/CE/CLK). That's a Phase 7 follow-on item, not the same shape of fix.

Context

This is the next bite of Phase 7 ("wafer.space test-run-1 design integration") in docs/plans/gf180mcu-enablement.md.

Test plan

• cargo test --lib gf180mcu — 59 passing locally
• CI green on main-based branch