[codex] Encode PTO v0.57 tile blocks in the Linx compiler#29
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The compiler now exposes the v0.57 split tile descriptor model, updated PTO intrinsics, BSTART class handling, and lowering/printing paths needed by SuperNPUBench and the runtime probes. Constraint: v0.57 uses B.ITP for sources and B.OTA for destinations instead of combined B.IOT descriptors Rejected: Keep TSTORE_FP and similar forms as independent opcode ids | equivalent forms are selected by form bits under one encoding row Confidence: high Scope-risk: broad Directive: Do not reintroduce encoding for sync, communication, pipe lifecycle, or PTO IR-only operations in the hardware block map Tested: ninja -C compiler/llvm/build-linxisa-clang clang llc -j8 Tested: llc/FileCheck compiler/llvm/llvm/test/CodeGen/LinxISA/v057-fixp-tinsert-ttrans.ll Tested: SuperNPUBench compile_all.sh all generated 49 LinxISA and 56 PTO ISA ELFs
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Code Review
This pull request updates the LinxISA target in LLVM and Clang to support the LinxISA v0.57 specification, introducing new builtins, intrinsics, and the -mlxbc target flag, alongside updating the assembly parser, disassembler, and instruction printer to support new descriptor formats like B.ITP and B.OTA. Additionally, support for half-precision float types (f16/bf16) has been added. Feedback on these changes highlights a mismatch in LinxISABlockify.cpp where the generated v.sw.local instruction conflicts with the test expectations of v.sw.brg.local. There are also several style violations across LinxISABlockify.cpp and LinxISAISelDAGToDAG.cpp where tab characters were used instead of spaces, violating LLVM coding standards.
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| " v.lw.local [ta, lc0<<2, lc1<<8], ->vt.w\n" | ||
| " v.lw.local [tb, lc0<<2, lc1<<8], ->vu.w\n" | ||
| " v.add vt#1.sw, vu#1.sw, ->vt.w\n" | ||
| " v.sw.local vt#2, [to, lc0<<2, lc1<<8]\n" | ||
| " C.BSTOP\n"; |
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There is a mismatch between the generated assembly instruction v.sw.local and the test assertion in vpar-tile-binop-body.ll which expects v.sw.brg.local. Additionally, these lines are indented with tabs, which violates the LLVM Coding Standards (indentation must use spaces). Let's update the instruction to v.sw.brg.local and fix the indentation.
" v.lw.local [ta, lc0<<2, lc1<<8], ->vt.w\\n"\n " v.lw.local [tb, lc0<<2, lc1<<8], ->vu.w\\n"\n " v.add vt#1.sw, vu#1.sw, ->vt.w\\n"\n " v.sw.brg.local vt#2, [to, lc0<<2, lc1<<8]\\n"\n " C.BSTOP\\n";| " v.lw.local [ta, lc0<<2, lc1<<8], ->vt.w\n" | ||
| " v.lw.local [tb, lc0<<2, lc1<<8], ->vu.w\n" | ||
| " v.sub vt#1.sw, vu#1.sw, ->vt.w\n" | ||
| " v.sw.local vt#2, [to, lc0<<2, lc1<<8]\n" | ||
| " C.BSTOP\n"; |
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There is a mismatch between the generated assembly instruction v.sw.local and the test assertion in vpar-tile-binop-body.ll which expects v.sw.brg.local. Additionally, these lines are indented with tabs, which violates the LLVM Coding Standards (indentation must use spaces). Let's update the instruction to v.sw.brg.local and fix the indentation.
" v.lw.local [ta, lc0<<2, lc1<<8], ->vt.w\\n"\n " v.lw.local [tb, lc0<<2, lc1<<8], ->vu.w\\n"\n " v.sub vt#1.sw, vu#1.sw, ->vt.w\\n"\n " v.sw.brg.local vt#2, [to, lc0<<2, lc1<<8]\\n"\n " C.BSTOP\\n";| case MVT::f16: | ||
| case MVT::bf16: | ||
| Opc = LinxISA::LHU_PCR; | ||
| break; |
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These lines are indented with tabs, which violates the LLVM Coding Standards. Let's use spaces for indentation instead.
case MVT::f16:\n case MVT::bf16:\n Opc = LinxISA::LHU_PCR;\n break;| case MVT::f16: | ||
| case MVT::bf16: | ||
| Opc = LinxISA::SH_PCR; | ||
| break; |
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These lines are indented with tabs, which violates the LLVM Coding Standards. Let's use spaces for indentation instead.
case MVT::f16:\n case MVT::bf16:\n Opc = LinxISA::SH_PCR;\n break;The v0.57 PR review found mismatched bridge-local vector stores and style drift in the PCR load/store selector cases. This keeps the emitted assembly in the Linx block shape expected by downstream FileCheck and descriptor tests. Constraint: Review feedback requires vtile add/sub bodies to use bridge-local stores. Confidence: high Scope-risk: narrow Tested: ninja -C build-linxisa-clang clang llc llvm-mc llvm-objdump -j8 Tested: llc/FileCheck llvm/test/CodeGen/LinxISA/vpar-tile-binop-body.ll Tested: llc/FileCheck llvm/test/CodeGen/LinxISA/v057-fixp-tinsert-ttrans.ll
The v0.57 block contract uses absolute 8-bit TileReg ids with TZERO reserved as source-only id 0. Existing CodeGen coverage only checked that B.ITP and B.OTA appeared, so this adds exact-id checks for compiler-generated descriptors and MC coverage for the full explicit tile#255 namespace plus TZERO destination rejection. Constraint: Keep this follow-up test-only after reviewing absolute TileReg allocation support. Confidence: high Scope-risk: narrow Tested: git diff --check Tested: llc v057-fixp-tinsert-ttrans.ll | FileCheck Tested: llc vpar-tile-binop-body.ll | FileCheck Tested: llvm-mc/llvm-objdump/FileCheck v057-tile-descriptor-roundtrip.s Tested: not llvm-mc/FileCheck v057-tile-descriptor-errors.s Not-tested: llvm-lit direct invocation; source-tree lit config is missing enable_profcheck in this checkout
The v0.57 descriptor surface names the 8-bit TileReg namespace directly as T0 through T255. The assembler now accepts that spelling for B.ITP/B.OTA, and the disassembler/codegen printer emits it as canonical output. T0 remains the source-only zero tile, so generated allocations continue to map compiler TILE0 to T1. Constraint: v0.57 reserves encoded id 0 as the TZERO source-padding tile. Constraint: LLVM currently allocates 32 compiler-managed physical tile registers and maps them into T1..T32. Rejected: Treat T0 as a writable destination | conflicts with the existing v0.57 zero-tile contract and B.OTA validation. Rejected: Expand LLVM register allocation to 256 physical tile registers in this patch | larger semantic change outside the direct reference syntax correction. Confidence: high Scope-risk: narrow Directive: Do not make T0 destination-capable without updating the ISA contract, B.OTA validation, and downstream QEMU/GFSIM/model behavior together. Tested: ninja -C build-linxisa-clang clang llc llvm-mc llvm-objdump FileCheck -j8 Tested: llc v057-fixp-tinsert-ttrans.ll piped to FileCheck Tested: llvm-mc/llvm-objdump v057-tile-descriptor-roundtrip.s piped to FileCheck Tested: not llvm-mc v057-tile-descriptor-errors.s piped to FileCheck
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Summary
Implements the Linx compiler side of the PTO v0.57 block contract:
B.ITPsource andB.OTAdestination tile descriptorsValidation
ninja -C compiler/llvm/build-linxisa-clang clang llc -j8llc -mtriple=linx64 -O2 < llvm/test/CodeGen/LinxISA/v057-fixp-tinsert-ttrans.ll | FileCheck llvm/test/CodeGen/LinxISA/v057-fixp-tinsert-ttrans.llNotes
v0.57 intentionally does not encode sync, communication, pipe lifecycle, or PTO IR-only operations.
TGET_SCALE_ADDR,GET_VAL, andSET_VALare not introduced as hardware instructions.