Update docs for 0.1.8: plain Verilog design support - #8
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Documents the new top-module disambiguation contract for hand-written .v designs (App/mrg.build/mrg CLI top= / --top), adds the Verilog Hello example, and backfills changelog entries for 0.1.7 (CloudSilicon board-less-submit fix) and 0.1.8. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
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Summary
App/mrg.build.synth/pnr/CLItop=/--topand the Wishbone port-contract used to auto-detect (or disambiguate) a plain-Verilog.vdesign's top moduleexamples/verilog_hello/in the SDK repo (nav + examples index updated)0.1.7(CloudSilicon board-less-submit fix) and0.1.8(Verilog support), which were missingTest plan
mkdocs build --strictpasses clean with the vendored_code/checkout updated to0.1.8reference/build.mdandreference/cloud.md(mkdocstrings-generated) render the newtopparameter automatically🤖 Generated with Claude Code