[codex] Port Jingtao V2 RVV model

[jensen-yan]

Motivation

This draft PR brings in the latest Tencent/Jingtao V2 RVV model as a reference branch for evaluating vector modeling against the current Kunminghu V3 direction.

Changes

• Port the Jingtao V2 RVV model onto xs-dev.
• Move the vector ISA generation path to the new banked RVV model.
• Add VLEN=256, DPLEN=128, VecBuf, banked vector register handling, and related O3 rename/regfile/scheduler support.
• Add design documentation for both the Jingtao V2 RVV port and the Kunminghu V3 RVV comparison.
• Enable gem5-vector.yml on this branch and add a no-difftest vector CI step.
• Fix an O3 pinned-write wakeup issue by marking final pinned writes bypass-ready before waking dependents.

Validation

• scons build/RISCV/gem5.opt --linker=gold -j64 --rvv-impl=simple passed locally.
• Local no-difftest RVV samples passed, including vmsltu.vx-2, vmsbc.vxm-1, vlsseg7e64.v-0, and vluxei8.v-0.
• CI run: https://github.com/OpenXiangShan/GEM5/actions/runs/27185002034
  • Build GEM5 opt: passed
  • run vector test without difftest: passed
  • run vector test: failed

Known Issues

The remaining vector CI failure is in difftest. Local reproduction shows the first vsetvli diverges because this branch models VLEN=256, while the current NEMU ref source/config uses VLEN=128. This branch should either use a matching 256-bit VLEN NEMU ref for Jingtao validation, or be treated as a no-difftest reference branch until the Kunminghu V3 VLEN=128 direction is implemented.

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[github-actions]

🚀 Coremark Smoke Test Results

Branch	IPC	Change
Base (xs-dev)	2.3168	-
This PR	2.3168	➡️ 0.0000 (0.00%)

✅ Difftest smoke test passed!

[jensen-yan]

/nfs/home/yanyue/Gem5-jiezi_v2_merge_kmhv3_202606

[github-actions]

🚀 Coremark Smoke Test Results

Branch	IPC	Change
Base (xs-dev)	2.3155	-
This PR	2.3155	➡️ 0.0000 (0.00%)

✅ Difftest smoke test passed!