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Test branch microprogram control flow
CI
#667:
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Add branch-family microprograms
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Test immediate ALU microprograms
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Add immediate ALU microprograms
CI
#664:
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Align M10.3 roadmap with qualified microcode work
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Mark M10.2 experimental I/O complete
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Record final M10.2 workflow qualification
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Tidy M10 I/O FPGA workflow triggers
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Mark M10.2 instruction and RTL bus definition complete
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Define experimental IN OUT encoding and RTL I/O bus
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PLS: use released v0.1.0 validator
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PLS smoke adoption: quote YAML language codes
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PLS smoke adoption: add pinned validation workflow
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PLS smoke adoption: add EduCPU metadata
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#654:
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Qualify stack-relative effective-address microcode
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Add stack-relative LOADS and STORES microprograms
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Regress STORER MAR lifetime across source fetch
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Fix STORER address-register sampling hazard
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Qualify register-indirect LOADR and STORER
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Add register-indirect LOADR and STORER microprograms
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Mark M10.2 software I/O semantics qualified
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Freeze qualified M10.2 software I/O semantics
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Guard STORE register-source selection
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Make REG_A source read selected register for STORE
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Guard LOAD STORE operand-order address assembly
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