Fix VCG group reduction semantics#889
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This pull request updates the documentation and specifications for per-VLane (group) reduction operations (pto.vcgadd, pto.vcgmax, and pto.vcgmin) to clarify that the 8 VLane results are written contiguously to the low elements (indices 0 to 7) of the destination vector, with the remaining elements zeroed out. It also adds a comprehensive micro-op test case to verify these operations. The feedback suggests explicitly clarifying the zero-filling behavior when the vector register is not fully populated (e.g., for larger element types like i64).
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| The vector register is organized as **8 VLanes** of 32 bytes each. Group | ||
| reductions operate within each VLane independently and produce one result per | ||
| VLane. The 8 VLane results are written contiguously to the low elements of the | ||
| destination vector; all remaining destination elements are zero. |
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The updated documentation states that group reductions produce one result per VLane and write them contiguously to the low elements of the destination vector. However, the documentation should explicitly clarify the behavior when the vector register is not fully populated (e.g., when the element type has fewer than 64 elements, such as i64 which has 32 elements). Please clarify if the remaining elements are always zero-filled up to the full vector register size N regardless of the element type.
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Summary
pto.vcgadd,pto.vcgmax, andpto.vcgminValidation
git diff --checkWORK_SPACE=/tmp/pto-vpto-vcg-group CASE_NAME='micro-op/reduction/vcg-group' DEVICE=SIM test/vpto/scripts/run_host_vpto_validation.sh