Escape Yosys-reserved words in Verilog

[jeet-dekivadia]

Summary

• use the IEEE 1800 keyword superset when legalizing Verilog identifiers so emitted netlists remain compatible with Yosys
• add the four current Yosys keywords missing from the SystemVerilog table and fix the untyped spelling
• update the RTL expect regression to cover the reported dist identifier in Verilog, SystemVerilog, and VHDL output

Fixes #21

Correctness

Yosys applies its SystemVerilog keyword table while emitting Verilog. Using the same superset for Hardcaml's Verilog legalization ensures names rejected by Yosys are escaped before they reach the backend. VHDL legalization is unchanged.

Validation

• git diff --check
• private Linux comparison script extracted Hardcaml's SystemVerilog table and Yosys verilog_keywords(): matched all 248 keywords with no missing or extra entries
• checked the focused expect fixture for escaped Verilog \dist declarations and assignments while VHDL remains dist
• full Dune validation could not start from the public source because the current dependency set includes unpublished package ppx_rope