Skip to content

Escape Yosys-reserved words in Verilog #30

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
jeet-dekivadia wants to merge 1 commit into
base: master
Choose a base branch
from

Escape Yosys-reserved words in Verilog

fc189a8
Select commit
Loading
Failed to load commit list.
Open

Escape Yosys-reserved words in Verilog #30

Escape Yosys-reserved words in Verilog
fc189a8
Select commit
Loading
Failed to load commit list.
DCO / DCO succeeded May 30, 2026 in 1s

DCO

All commits are signed off!

View more details on DCO