30-day VLSI & Digital Design learning journey — Verilog, FSM, FPGA, UART
A structured 30-day roadmap to learn VLSI & Digital Design from scratch — built as part of placement preparation.
- 3rd Year ECE Student
- Targeting core VLSI companies (Qualcomm, Intel, TI)
- Tools: Verilog HDL, Xilinx Vivado, EDA Playground
- ✅ Boolean Algebra & Logic Gates
- ✅ K-Map Simplification
- ✅ Combinational Circuits (MUX, Decoder, Encoder)
- ✅ Arithmetic Circuits (Adders, Subtractor, BCD)
- ✅ Verilog HDL — Modelling styles, Testbench, Module instantiation
- ✅ Sequential Logic — Flip-Flops, Counters, Shift Registers
- ✅ FSM Design — Moore FSM, 3-block style, Traffic Light Controller
- ✅ UART Protocol — TX, RX, Loopback verified
- ✅ SystemVerilog — logic, always_ff, always_comb, enum
| Project | Status | Tools |
|---|---|---|
| 4-bit Ripple Carry Adder | ✅ Done | Verilog, EDA Playground |
| Traffic Light FSM | ✅ Done | Verilog, EDA Playground |
| 4-bit ALU | ✅ Done | Vivado 2023.2, Artix-7 |
| UART complete Module | ✅ Done | Verilog, Vivado 2023.2 |
Started: June 2026 | Target: 30 days
vlsi-learning/ ├── week1-digital-logic/ │ ├── rca_4bit.v │ └── tb_rca_4bit.v ├── week2-sequential/ │ ├── traffic_light_fsm.v │ └── tb_traffic_light_fsm.v ├── week3-fpga/ │ ├── alu_4bit.v │ ├── tb_alu_4bit.v │ └── alu_constraints.xdc └── week4-protocols/ ├── uart_tx.v ├── uart_rx.v ├── uart_top.v ├── tb_uart_complete.v └── uart_constraint.xdc
| Tool | Purpose |
|---|---|
| Verilog HDL | RTL Design |
| SystemVerilog | Advanced RTL |
| EDA Playground | Browser simulation |
| Xilinx Vivado 2023.2 | Synthesis, P&R, Bitstream |
| Artix-7 FPGA | Target device |
Started: June 2026 | Completed: August 2026