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nselvara / chipdev.io

This repository contains VHDL implementations for all hardware design challenges (quests/questions) featured on the chipdev.io website.

simulation vhdl hdl testbenches osvvm vunit vhdl-code vhdl-examples vhdl2008 vhdl-testbench chipdev vhdl-2008 eda-playground

Updated Jan 2, 2026
VHDL

nselvara / HDL-Core-Library

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Reusable HDL modules, packages, and testbench utilities for FPGA and ASIC development, supporting both VHDL and Verilog.

simulation vhdl rtl hdl testbenches osvvm vunit vhdl-modules vhdl-code vhdl2008 vhdl-testbench vhdl-2008 eda-playground

Updated Jan 5, 2026
VHDL

nselvara / VHDL-Utils

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A VHDL code base that contains Utility Packages for both HDL and Testbenches

simulation vhdl rtl hdl testbenches osvvm vunit vhdl-modules vhdl-code vhdl2008 vhdl-testbench vhdl-2008 eda-playground vhdl-2019 vhdl2019

Updated Aug 19, 2025
VHDL

vinaybongale-16 / 4-bit-ALU-Verilog

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4-bit ALU design and simulation using Verilog HDL

verilog digital-logic alu hdl vlsi verilog-hdl digital-design eda-playground 4-bit-alu epwave

Updated Aug 24, 2026
Verilog

aryan-yadav4149 / 4Bit-Alu-Yosys-Symthesis

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4-bit ALU RTL to Gate-Level Synthesis using Yosys + ABC on EDA Playground

mapping system-verilog yosys digital-design vlsi-design open-source-eda rtl-synthesis abc-tech eda-playground 4bit-alu

Updated Jun 5, 2026
SystemVerilog

panoskoutris / riscv-cpu

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Fully functional RISC-V compatible multicycle CPU built in Verilog. Includes ALU, datapath, FSM controller, memory, and testbenches.

fsm fpga hardware simulation verilog computer-architecture icarus-verilog hdl testbench risc-v digital-design processor-design cpu-design eda-playground

Updated Aug 17, 2025
Verilog

Divyanshukumar2005 / Different-ways-to-implement-mux-in-verilog

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Multiplexer (2:1, 4:1, 8:1) designs in Verilog HDL using case, if-else & ternary styles — simulated with Icarus Verilog and synthesized with Yosys on EDA Playground.

verilog mux icarus-verilog multiplexer verilog-hdl yosys digital-design hardware-description-language combinational-logic verilog-programs verilog-project verilog-code rtl-design eda-playground

Updated Sep 11, 2026
Verilog

Tharunreddym / axi4-verification

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AXI4 Memory Controller UVM Verification Environment with real Siemens Questa seed-1 simulation logs, scoreboard checks, functional coverage summaries, and documented burst-read debug fix.

python scoreboard regression-testing systemverilog uvm constrained-random semiconductor digital-design sva questa axi4 functional-coverage rtl-verification eda-playground

Updated May 19, 2026
SystemVerilog

spunkycurative / fifo_design_verification_sv

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SystemVerilog verification of an 8-bit × 16 synchronous FIFO using a class-based testbench, scoreboard, and 10+ SVA assertions.

verilog systemverilog fifo testbench digital-design sva design-verification systemverilog-assertions eda-playground

Updated Jul 11, 2026
SystemVerilog

Tharunreddym / sram-uvm-verification

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SRAM subsystem verification using SystemVerilog UVM, SVA assertions, scoreboard, functional coverage, and 20-seed QuestaSim regression evidence from EDA Playground.

assertions scoreboard sram regression-testing systemverilog uvm constrained-random digital-design questa functional-coverage eda-playground verification-environment

Updated May 19, 2026
SystemVerilog

aryan-yadav4149 / 4bit-ALU

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Implementation of 4-bit Arithmetic Logic Unit using structural modeling in Verilog. Features 8 operations controlled by 3-bit select line. Simulated on EDA Playground with waveform analysis.

fgpa digitalelectronics eda-playground verilog-alu

Updated May 22, 2026
Verilog

Muniem-Amjad / MIPS-pipeline

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5-stage MIPS pipeline CPU in Verilog with data forwarding, hazard detection and full instruction set. Simulated on EDA Playground.

cpu pipeline mips verilog computer-architecture hazard-detection icarus-verilog hdl digital-design data-forwarding eda-playground

Updated May 24, 2026
Verilog

dalimkumar452-sudo / VLSI-Digital-Clock-UART-Dashboard

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Advanced VLSI Digital Clock in Verilog (RTL) featuring hardware debouncing, alarm FSM, and a real-time Python/Tkinter GUI dashboard via UART.

fpga rtl verilog tkinter uart vlsi digital-design python-dashboard hardware-software-codesign eda-playground

Updated Jun 21, 2026
Verilog

beemashahanashiyad / UART-Communication-System-Verilog

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UART communication system in Verilog featuring transmitter, receiver, baud rate generator, self-checking testbench, and comprehensive verification using EDA Playground.