[RISCV][Lifting] Implement the F and D extensions (floating and double floating point) in RISC-V, implement CSR instructions for fflags

[moste00]

Your checklist for this pull request

• I've read the guidelines for contributing to this repository.
• I made sure to follow the project's coding style.
• I've documented every RZ_API function and struct this PR changes.
• I've added tests that prove my changes are effective (required for changes to RZ_API).
• I've updated the Rizin book with the relevant information (if needed).
• I've used AI tools to generate fully or partially these code changes and I'm sure the changes are not copyrighted by somebody else.

Detailed description

Continues #6373. Implements the F and D extensions of RISC-V.

Claude Code CLI was used to write some of the code here, I take full responsiblity for all code in this PR as fully mine.

Test plan

As with the I (integer) and M extensions, the F and D extensions were tested using tracetesting. For now, I didn't run any real-world binaries like ls or grep yet, but I ran simple minimal binaries and made sure no execution mismatches between the lifting and usermode QEMU occur.

The ultimate goal before merging this PR is that arbitrary ELF binaries like GNU utilities would run with no machine state mismatches betweeen QEMU and Rizin.

Closing issues

PR Stack Structure

This PR is the fourth of a 4-PR stack that lifts the IMAFD RISC-V archiecture plus some privileged instructions.

The following is a table for ease of navigation from any PR to any other, please filter by the commit(s) mentioned in the table when reviewing the diff in the "Files Changed" tab to avoid the noise of the base branches.

Extension	PR	Commits To Select in "Files Changed"	State (Open, Merged, Draft, Closed)
I	#6287	No filtering necessary	O
M	#6364	"implement the rest of the multiplication extension"	D
A	#6373	"implement the atomic extension trivially by ignoring concurrency guards"	D
F/D	#6374 < (THIS PR)	"add floating and double instructions, and add privlieged ISA instructions like reading CSRs to implement fflags reading and writing"	D

Because it's painful to maintain this stack manually with no Github or other tooling support, I won't grow it any further until one of those 4 PRs gets merged.

Depends-on: #6373