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@ryanbreen ryanbreen commented Jan 11, 2026

Summary

  • Consolidate all inline assembly in per_cpu.rs to use HAL trait calls via X86PerCpu
  • Add two HAL-specific boot stage markers (HAL_PERCPU_INITIALIZED, HAL_TIMER_CALIBRATED) for CI validation
  • Reduce ~500 lines of inline assembly to HAL calls, improving portability

Validation Fixes (Latest Commit)

Address issues found during technical implementation validation:

  1. HAL Read-back Verification - Added verification in per_cpu::init() that confirms GS-relative operations work correctly (tests cpu_id and preempt_count cycle)

  2. Offset Constant Consolidation - Removed duplicate offset constants, now uses offset_of! compile-time assertions against HAL constants (13 field assertions)

  3. Debug Underflow Assertions - Added debug-only underflow checks in irq_exit, nmi_exit, softirq_exit

  4. Compiler Fence Consistency - Added fences to irq_enter/irq_exit matching other interrupt context functions

  5. NMI_MASK Bug Fix - Fixed from 0x3 << 26 (2 bits, wrong) to 0x1 << 26 (1 bit, correct per Linux kernel)

  6. Documentation Fix - Updated preempt_count bit layout comment to match actual implementation

Changes

per_cpu.rs Consolidation

All per-CPU operations now go through the HAL:

  • Thread management: current_thread, set_current_thread
  • Stack management: kernel_stack_top, set_kernel_stack_top
  • Preemption: preempt_disable, preempt_enable, preempt_count
  • Interrupt context: in_interrupt, irq_enter/exit, nmi_enter/exit
  • Softirq handling: softirq_pending, raise_softirq, clear_softirq
  • CR3 management: get/set_next_cr3, get/set_kernel_cr3
  • Exception cleanup context functions

Boot Stage Markers

  • HAL_PERCPU_INITIALIZED - Emitted when per-CPU data is initialized
  • HAL_TIMER_CALIBRATED - Emitted when TSC calibration completes

Test plan

  • Build passes with no new warnings
  • Boot stages test: 140/140 passing
  • All syscalls continue to work (clock_gettime, fork, etc.)
  • Timer interrupts fire correctly
  • Context switching works
  • Technical validation passed (scores: Technical Accuracy A, Intellectual Honesty A)

🤖 Generated with Claude Code

- Replace all inline assembly in per_cpu.rs with HAL trait calls
- Thread management: current_thread, set_current_thread via X86PerCpu
- Stack management: kernel_stack_top, set_kernel_stack_top via HAL
- Preemption: preempt_disable/enable/count via PerCpuOps trait
- Interrupt context: in_interrupt, irq_enter/exit, nmi_enter/exit
- Softirq handling: softirq_pending, raise_softirq, clear_softirq
- CR3 management: get/set_next_cr3, get/set_kernel_cr3
- Exception cleanup: all context functions via HAL
- Add HAL_PERCPU_INITIALIZED boot stage marker
- Add HAL_TIMER_CALIBRATED boot stage marker

This reduces ~500 lines of inline assembly to HAL calls, improving
portability for future ARM64 support while maintaining zero overhead
through #[inline(always)] trait methods.

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
@ryanbreen ryanbreen force-pushed the feature/hal-abstraction-phase2 branch from 1db69bd to c32bdcb Compare January 11, 2026 12:51
ryanbreen and others added 2 commits January 11, 2026 18:43
Address validation issues from HAL Phase 2 review:

- Add read-back verification in per_cpu::init() to confirm HAL operations
  work correctly (tests cpu_id and preempt_count read/write cycle)
- Consolidate offset constants to single source of truth using offset_of!
  compile-time assertions against HAL constants
- Add debug-only underflow assertions in irq_exit, nmi_exit, softirq_exit
- Add compiler fences to irq_enter/irq_exit for consistency with other
  interrupt context functions
- Fix NMI_MASK from 0x3 << 26 (2 bits, wrong) to 0x1 << 26 (1 bit, correct
  per Linux kernel)
- Fix preempt_count bit layout documentation to match actual implementation

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
@ryanbreen ryanbreen merged commit adcc5e0 into main Jan 12, 2026
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2 participants