feat(hal): Consolidate per_cpu.rs to use HAL exclusively

kernel/src/arch_impl/x86_64/constants.rs

@@ -182,7 +182,7 @@ pub const SOFTIRQ_SHIFT: u32 = 8;
 /// Shift for HARDIRQ field (bits 16-25).
 pub const HARDIRQ_SHIFT: u32 = 16;
 
-/// Shift for NMI field (bits 26-27).
+/// Shift for NMI field (bit 26 only - Linux uses 1 bit for NMI).
 pub const NMI_SHIFT: u32 = 26;
 
 /// Bit position for PREEMPT_ACTIVE flag.
@@ -197,8 +197,8 @@ pub const SOFTIRQ_MASK: u32 = 0xFF << SOFTIRQ_SHIFT;
 /// Mask for HARDIRQ field.
 pub const HARDIRQ_MASK: u32 = 0x3FF << HARDIRQ_SHIFT;
 
-/// Mask for NMI field.
-pub const NMI_MASK: u32 = 0x3 << NMI_SHIFT;
+/// Mask for NMI field (1 bit only, matching Linux kernel).
+pub const NMI_MASK: u32 = 0x1 << NMI_SHIFT;
 
 /// PREEMPT_ACTIVE flag value.
 pub const PREEMPT_ACTIVE: u32 = 1 << PREEMPT_ACTIVE_BIT;

kernel/src/arch_impl/x86_64/percpu.rs

@@ -238,23 +238,35 @@ impl X86PerCpu {
     /// Enter hard IRQ context (increment HARDIRQ count).
     #[inline(always)]
     pub unsafe fn irq_enter() {
+        // Compiler barrier before incrementing - ensures all prior operations complete
+        // before we mark ourselves as being in interrupt context
+        compiler_fence(Ordering::Acquire);
         asm!(
             "add dword ptr gs:[{offset}], {inc}",
             offset = const PERCPU_PREEMPT_COUNT_OFFSET,
             inc = const (1 << HARDIRQ_SHIFT),
             options(nostack, preserves_flags)
         );
+        // Compiler barrier after incrementing - ensures the context transition is
+        // visible before any interrupt handling code runs
+        compiler_fence(Ordering::Release);
     }
 
     /// Exit hard IRQ context (decrement HARDIRQ count).
     #[inline(always)]
     pub unsafe fn irq_exit() {
+        // Compiler barrier before decrementing - ensures all interrupt handling
+        // operations complete before we exit interrupt context
+        compiler_fence(Ordering::Acquire);
         asm!(
             "sub dword ptr gs:[{offset}], {dec}",
             offset = const PERCPU_PREEMPT_COUNT_OFFSET,
             dec = const (1 << HARDIRQ_SHIFT),
             options(nostack, preserves_flags)
         );
+        // Compiler barrier after decrementing - ensures the context transition is
+        // visible before we potentially reschedule or return to interrupted code
+        compiler_fence(Ordering::Release);
     }
 
     /// Set the PREEMPT_ACTIVE flag.

kernel/src/arch_impl/x86_64/timer.rs

@@ -189,6 +189,9 @@ pub fn calibrate() {
             CALIBRATION_MS,
             tsc_elapsed
         );
+
+        // HAL boot stage marker - proves HAL timer operations are working
+        log::info!("HAL_TIMER_CALIBRATED: TSC calibration via HAL complete");
     }
 }