design-rule-check

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the Design Rule Check (DRC) violation location.

Design-rule check: a GDS layout + a rule deck in, geometry violations out.

Design rule checker for VLSI layouts

Citation-grounded RAG assistant for semiconductor PDK/EDA engineers. Answers design-rule questions and drafts DRC/LVS snippet pseudocode, grounded in public PDK docs with a built-in citation guard.

Design Rule Check engine for auto-generated diagrams — crossing minimization, spacing, label overlap detection and auto-fix

Designed and implemented a low-power hybrid full adder and 4-bit/8-bit array multipliers in GPDK 90nm CMOS using Cadence Virtuoso, including schematic design, full-custom layout, DRC/LVS verification, PEX, and post-layout performance analysis.

Complete KiCad PCB design of a 5V to 3.3V linear voltage regulator using AMS1117-3.3, with schematic, two-layer PCB layout, routing, and 0 DRC violations.

Designed and implemented a performance-balanced noise-canceling LNA in SCL 180nm CMOS using Cadence Virtuoso, covering CG-CS, Cascode, and Folded-Cascode architectures, RF analysis, full-custom layout, DRC/LVS, PEX, and a custom spiral inductor.

Hands-on Analog Layout Internship/Training at Semionics using Cadence Virtuoso and GlobalFoundries 40nm, covering custom analog, mixed-signal, and CMOS circuit layout.