parasitic-extraction

First-principles EM field simulation for analog and digital circuits. Quasi-static + drift-diffusion + electro-thermal + SPICE on one Yee grid, with exact field-circuit coupling. Every assumption documented and measured.

Hands-on Analog Layout Internship/Training at Semionics using Cadence Virtuoso and GlobalFoundries 40nm, covering custom analog, mixed-signal, and CMOS circuit layout.

Designed and implemented a performance-balanced noise-canceling LNA in SCL 180nm CMOS using Cadence Virtuoso, covering CG-CS, Cascode, and Folded-Cascode architectures, RF analysis, full-custom layout, DRC/LVS, PEX, and a custom spiral inductor.

Does your coupling extractor predict physics that cannot exist? Detects anti-screening (k>1), which no passive arrangement of conductors can produce.

RC parasitic extraction — routed layout to SPEF; a calibrated sky130 deck tracks OpenRCX.