Developing a fixed-point Softmax Processing Unit for DNN accelerators using LUT-based exponentiation and an 8-stage pipelined Mitchell divider. Implemented in Verilog and completed RTL-to-GDSII on TSMC 180nm (Cadence). Achieves 8.9× throughput improvement with 97.89% MNIST accuracy. SCI journal in progress.
cts verilog-hdl gdsii physical-design fixed-point-arithmetic cadence-innovus cadence-genus tsmc-180nm spef-extraction dnn-inference-hardware
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Updated
Apr 3, 2026