Developing a fixed-point Softmax Processing Unit for DNN accelerators using LUT-based exponentiation and an 8-stage pipelined Mitchell divider. Implemented in Verilog and completed RTL-to-GDSII on TSMC 180nm (Cadence). Achieves 8.9× throughput improvement with 97.89% MNIST accuracy. SCI journal in progress.

Low-power fixed-point Softmax processing unit with LUT-based exponentiation and an 8-stage pipelined Mitchell logarithmic divider. Designed in Verilog and implemented on TSMC 180nm using Cadence tools. Achieves 1 output/cycle throughput and 8.9× speedup over sequential division. Patent under review.

Adaptive Quadrant (AQ) reconfigurable 16-bit multiplier using quadrant decomposition and row bypassing for low-power operation. Implemented in RCA and hybrid prefix adder variants across TSMC 180nm/90nm using Cadence tools. Achieves significant power and area reduction with scalable architecture. SCI journal manuscript under review.

Dynamic reconfigurable binary multiplier using quadrant decomposition and adaptive row bypassing for scalable, low-power operation. Designed in Verilog and implemented on TSMC 180nm/90nm using Cadence tools. Published Indian patent (202541080342).