I have built a R-type and I-type datapath for a 16-bit system in logisim, featuring 16 bit data, 4-bit addressing (16 registers) and 16-bit instructions, where the ALU is capable of performing 8 operations. More descriptions are written inside the file

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A parameterized Verilog Register File featuring synchronous write, dual asynchronous read ports, configurable data width and memory depth, along with a comprehensive testbench for functional verification.

Solutions of Computer Architecture Labs using verilog.