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feat(fpga): add Rev A ECP5UM-45F P&R target
FPGA qualification
#53:
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feat(fpga): add Rev A ECP5UM-45F P&R target
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feat(fpga): add Rev A ECP5UM-45F P&R target
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#51:
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feat(fpga): add board-neutral RetroCore RTL skeleton
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feat(fpga): add board-neutral RetroCore RTL skeleton
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fix(ci): install Icarus before RetroCore RTL tests
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feat(fpga): add board-neutral RetroCore RTL skeleton
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docs(fpga): clarify synthetic 85K CI target
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ci(fpga): distinguish synthetic 85K smoke from Rev A target
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feat(fpga): add board-neutral RetroCore RTL skeleton
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feat(fpga): add board-neutral RetroCore RTL skeleton
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feat(fpga): add board-neutral RetroCore RTL skeleton
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feat(fpga): add board-neutral RetroCore RTL skeleton
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feat(fpga): add board-neutral RetroCore RTL skeleton
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M3.2: implement SDRAM timing guards
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M3.2: implement SDRAM timing guards
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#38:
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m3-2-sdram-timing
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M3.2: encode datasheet-based SDRAM timing guards
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M3.2: fix SDRAM precharge policy
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M3.2: fix SDRAM precharge policy
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M3.2: assert explicit-precharge SDRAM policy
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M3.2: use explicit precharge policy for SDRAM accesses
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M3.2: qualify SDRAM controller protocol
FPGA qualification
#32:
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M3.2: qualify SDRAM controller protocol
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m3-2-sdram-simulation
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M3.2: synchronize SDRAM test traffic to initialized idle state
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M3.2: qualify SDRAM controller protocol
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