Dynamic reconfigurable binary multiplier using quadrant decomposition and adaptive row bypassing for scalable, low-power operation. Designed in Verilog and implemented on TSMC 180nm/90nm using Cadence tools. Published Indian patent (202541080342).
verilog-hdl cadence-innovus rtl-to-gdsii cadence-genus tsmc-180nm tsmc-90nm low-power-vlsi digital-arithmetic-circuits
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Updated
Apr 2, 2026