SARV A Risc-V
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Updated
Sep 16, 2026 - Verilog
SARV A Risc-V
A comprehensive collection of digital design and computer architecture interview questions. Features detailed mathematical derivations, hardware schematics, and FSM state diagrams covering BCD logic, binary arithmetic, and sequential circuits.
FPGA-implemented RISC-V processor, evolved from single-cycle to 5-stage pipelined architecture for higher performance and timing efficiency. BRAM-based instruction memory optimizes FPGA usage. Fully FPGA-ready, general-purpose yet tailorable for any AI application, demonstrated with an ML heart rate anomaly detector for wearable AI.
An open source, modular 32-bit RISC-V System-on-Chip (SoC) built around the SARV processor core, featuring caches, ACLINT, PLIC, UART, and GPIO.
Pipelined artificial neuron with ReLU activation — synthesized and hardware-validated on Xilinx Artix-7 FPGA (Basys 3)
a 4-bit gate-level ALU designed using basic logic gates, with Verilog implementation and testbench verification.
Embedded Systems · IoT · Firmware · Digital Design
RISC V Single Cycle Processor
Formally verified, synthesis-ready 8-bit RISC CPU in Verilog. Optimized for efficient hardware implementation.
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