Parameterized 16-bit ALU designed in Verilog HDL with functional verification, synthesis, RTL schematic, and gate-level netlist.
lint verilog vlsi verilator rtl-design-and-verification rtl-design-and-simulation yosys-synthesis rtl-schematic gate-level-schematic parameterized-16-bit-alu rtl-design-verification
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Updated
Jul 3, 2026 - Verilog