4-bit Arithmetic Logic Unit in Verilog with carry-out, overflow and zero flags derived directly from the arithmetic path. Verified with a self-checking testbench targeting flag edge cases, plus gate-level synthesis via Yosys to confirm it's real synthesizable RTL.
verilog computer-architecture alu icarus-verilog verilog-hdl yosys digital-design hardware-description-language verilog-programs verilog-project verilog-code rtl-design rtl-design-and-verification rtl-design-project-using-verilog-hdl rtl-design-and-simulation hardware-description-languages digital-design-repo rtl-design-verification
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Updated
Sep 11, 2026 - Verilog