rtl-design-and-simulation

RTL Design and Verification of a Parameterized Synchronous FIFO in Verilog with directed, corner, and randomized test cases.

4-bit Arithmetic Logic Unit in Verilog with carry-out, overflow and zero flags derived directly from the arithmetic path. Verified with a self-checking testbench targeting flag edge cases, plus gate-level synthesis via Yosys to confirm it's real synthesizable RTL.

FPGA-based Adaptive Sensor Controller designed using Verilog HDL and implemented using Xilinx Vivado. The design monitors sensor activity and dynamically classifies input data into different activity levels.

This project presents a scalable, high-performance VLSI router architecture for Network-on-Chip (NoC) platforms, using Code Division Multiple Access (CDMA) to enable concurrent data transfers with reduced latency and power consumption. Built with Verilog HDL and implemented on an Artix-7 FPGA.

This specialized engineering repository serves as a production-ready development workspace for synthesizable Register-Transfer Level (RTL) Design and advanced hardware verification architectures utilizing Verilog HDL (IEEE 1364-2005). Decoupled from generic high-level software environments, this repository is explicitly engineered to demonstrate in

Parameterized 16-bit ALU designed in Verilog HDL with functional verification, synthesis, RTL schematic, and gate-level netlist.

5-Stage RISC-V Pipelined Processor designed in Verilog HDL featuring Instruction Fetch, Decode, Execute, Memory Access, and Write-Back stages with RTL simulation and verification.

8-bit ALU RTL design and verification in SystemVerilog — self-checking testbench, SVA assertions, functional coverage

RTL design and functional verification of a 32-bit ALU using Verilog HDL. Supports arithmetic, logical, and shift operations with corner-case handling such as divide-by-zero, underflow, and tri-state output enable. Simulated and verified using Xilinx ISE.

FPGA-based smart home automation controller using Verilog HDL featuring automated lighting, temperature-based appliance control, security alarm logic, and simulation-based verification.

Configurable AXI arbiter (Round Robin / Fixed Priority + Aging) — RTL verified in Vivado, implemented on Xilinx Artix-7, UVM testbench verified on Xcelium 25.03

This repository contains our project on 4-2 Compressor and 3-2 Compressor based 8x8 Dadda Multiplier

This repository contains the report of the Week 3 task for VSD RV SoC Tapeout Program

A collection of 5 RTL digital design modules implemented in Verilog and simulated using ModelSim — covering UART, FIFO, Traffic Light Controller, Automatic Temperature Control, and Washing Machine Controller, each designed using FSM-based architecture with draw.io block diagrams, state transition tables, and waveform verification.