ICRTL Benchmark: Industrial-level RTL design challenges for evaluating PPA optimization, code generation, and LLM applications in EDA.
benchmark evolution natural-language ppa eda rtl verilog system-verilog yosys ic-design vlsi-design rtl-design hardware-accelerator ai-agent verilogeval rtllm llm-benchmark spec-to-rtl
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Updated
Jun 28, 2026 - SystemVerilog