[DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers
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Jul 9, 2025 - Verilog
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verilogeval
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This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation
reinforcement-learning hardware eda verilog code-generation llama hdl research-paper verilog-hdl reasoning verilog-code testbench-generator-verilog large-language-models llm rlhf ai4eda qwen verilogeval reasoning-language-models openr1
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Sep 25, 2025 - Python
ICRTL Benchmark: Industrial-level RTL design challenges for evaluating PPA optimization, code generation, and LLM applications in EDA.
benchmark evolution natural-language ppa eda rtl verilog system-verilog yosys ic-design vlsi-design rtl-design hardware-accelerator ai-agent verilogeval rtllm llm-benchmark spec-to-rtl
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Jun 28, 2026 - SystemVerilog
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