systemverilog-constraint

RV32I RISC-V core written in SystemVerilog, with an emphasis on coverage-driven verification using constrained-random stimulus, SVA assertions, and functional coverage

cpu fpga verification assertions riscv rtl vivado systemverilog risc-v rv32i design-verification constrained-random-verification cpu-simulation functional-coverage systemverilog-assertions systemverilog-constraint

Updated Jun 4, 2026
SystemVerilog

Karan-nevage / Systemverilog-Constraints-Interview-Questions

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A structured collection of SystemVerilog constraint randomization problems and solutions. Organized by difficulty levels theoretical easy medium and hard coding to support progressive learning. Designed for mastering constraint techniques building reusable SV UVM examples and preparing for Design Verification interviews.

constraints systemverilog constrained-random-verification systemverilog-constraint system-verilog-interview-prepration

Updated Feb 17, 2026
SystemVerilog

HastiNavab / Gray-Code-Counter

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A 4-bit Gray code counter designed in Digital and implemented in SystemVerilog with testbench verification.

counter finite-state-machine digital-logic systemverilog hardware-designs testbench systemverilog-hdl sequential-logic digital-logic-design gray-code 4-bit systemverilog-simulation 4-bits-mode systemverilog-test-bench systemverilog-language systemverilog-constraint sequential-logic-circuit gray-counter

Updated Sep 2, 2026
Verilog

raviranjan-vlsi / UART-Protocol-Verification-

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End-to-end UART TX/RX verification using SystemVerilog OOP, constrained-random stimulus, functional coverage, SVA assertions, mailboxes, monitors, drivers, and self-checking scoreboards.

Updated Sep 10, 2026
SystemVerilog

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