Systemverilog and UVM exercises inspired by ziglings
UART verification using UVM with functional coverage, scoreboard, and test scenarios, simulated on QuestaSim.
UVM-based verification environment for an APB FIFO design with comprehensive test coverage and bug analysis.
Hands-on Design Verification — SystemVerilog testbenches, full UVM environment for APB Protocol, Python scripting, SVA assertions & functional coverage. Trained at ChipEdge using Synopsys VCS.
Custom 16-bit 3-stage pipelined CPU in SystemVerilog with UVM verification, RAW hazard handling, assertions, constrained-random testing, and functional coverage.
UVM-based verification environment for RISC-V Bit Manipulation Unit (BMU) covering key BitManip instructions
Synchronous FIFO verified using UVM including functional coverage
A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.
Low-Power CGRA Design Methodology (WIP)
MicroBlaze + AXI4-Lite 기반 SoC — Custom AXI I2C Master IP 설계, Reaction Test 앱(HW/SW Co-Design), UVM 검증(Functional Coverage 100%)
UVM testbench for an AXI4-Lite to UART bridge with multi-agent environment, UVM RAL, functional coverage, SVA, negative testing, and Makefile-based regression.
UVM-based functional verification environment for a 1x3 packet router using SystemVerilog — includes driver, monitor, scoreboard, sequences, and coverage.
SPI/I2C Master-Slave RTL 설계 및 UVM 기반 검증 — Scoreboard PASS, Functional Coverage 100%, Logic Analyzer 실측 검증 포함
UVM-based register verification environment using explicit predictor
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