A vector dot-product accelerator implemented in SystemVerilog and Anvil HDL, with SVA-based verification and matched-stimulus differential testing to explore Anvil’s timing-safety guarantees.
fpga accelerator anvil digital-design sva dot-product hardware-verification rtl-design formal-verification-methods systemverilog-language hardware-description-languages timing-safety
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Updated
Aug 31, 2026 - SystemVerilog