hardware-description-languages

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Divyanshukumar2005 / 4-bit-ALU-with-Status-Flags

4-bit Arithmetic Logic Unit in Verilog with carry-out, overflow and zero flags derived directly from the arithmetic path. Verified with a self-checking testbench targeting flag edge cases, plus gate-level synthesis via Yosys to confirm it's real synthesizable RTL.

verilog computer-architecture alu icarus-verilog verilog-hdl yosys digital-design hardware-description-language verilog-programs verilog-project verilog-code rtl-design rtl-design-and-verification rtl-design-project-using-verilog-hdl rtl-design-and-simulation hardware-description-languages digital-design-repo rtl-design-verification

Updated Sep 11, 2026
Verilog

IntikhabKhursheed / anvil-vector-dot-product

Star

A vector dot-product accelerator implemented in SystemVerilog and Anvil HDL, with SVA-based verification and matched-stimulus differential testing to explore Anvil’s timing-safety guarantees.

fpga accelerator anvil digital-design sva dot-product hardware-verification rtl-design formal-verification-methods systemverilog-language hardware-description-languages timing-safety

Updated Aug 31, 2026
SystemVerilog

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