synchronous-fifo

Here are 9 public repositories matching this topic...

umeshchess / sync-fifo-verilog

Synchronous FIFO

linux fedora verilog fifo vlsi verilog-project vlsi-design design-verification verilog-code vlsi-project fedora-linux design-verification-project synchronous-fifo

Updated Aug 10, 2026
Verilog

KushalPitaliya / Spartan6-Synchronous-FIFO

Star

A hardware-verified 8-bit Synchronous FIFO implemented on Xilinx Spartan-6 FPGA using Verilog HDL. Features robust signal debouncing, power-on reset logic, and real-time status monitoring.

fpga hardware verilog xilinx systemverilog fifo testbench digital-design spartan-6 synchronous-fifo

Updated Apr 15, 2026
SystemVerilog

rohit-kumarpanda / fifo-verilog

Star

Parameterized Synchronous and Asynchronous FIFO implementations in Verilog HDL with Gray-code pointer synchronization, CDC handling, and Vivado verification.

verilog fifo cdc vlsi verilog-hdl digital-design xilinx-vivado gray-code clock-domain-crossing asynchronous-fifo rtl-design synchronous-fifo

Updated Jul 29, 2026
Verilog

HemanjanaKumariKorrapati / Parameterized_Synchronous_FIFO

Star

RTL Design and Verification of a Parameterized Synchronous FIFO in Verilog with directed, corner, and randomized test cases.

lint verilog gtkwave fifo vlsi yosys iverilog icarus verilator hardware-design rtl-design-and-verification rtl-design-and-simulation synchronous-fifo

Updated Jul 4, 2026
Verilog

k-pitaliya / Spartan6-Synchronous-FIFO

Star

A hardware-verified 8-bit Synchronous FIFO implemented on Xilinx Spartan-6 FPGA using Verilog HDL. Features robust signal debouncing, power-on reset logic, and real-time status monitoring.

fpga hardware verilog xilinx systemverilog fifo testbench digital-design spartan-6 synchronous-fifo

Updated May 16, 2026
SystemVerilog

shreelakshmiKR / FIFO_Verilog

Star

Synchronous FIFO implementation in Verilog with testbench and simulation waveforms

verilog fifo hdl digital-design rtl-design eda-playground synchronous-fifo

Updated May 21, 2026
Verilog

Yaswanthreddy-696 / Synchronous-FIFO-Verilog

Star

RTL implementation of a parameterized synchronous FIFO in Verilog HDL with read/write operations, full and empty flag generation, overflow and underflow detection, and comprehensive testbench simulation using ModelSim.

asic fpga verilog fifo vlsi modelsim verilog-hdl rtl-design degital-design synchronous-fifo

Updated Jul 10, 2026
Verilog

jaswanthpj3 / synchronous-fifo-verilog

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Parameterized Synchronous FIFO in Verilog with Producer/Consumer testbench and GTKWave simulation.

rtl verilog fifo digital-design verilog-project rtl-design synchronous-fifo

Updated Aug 11, 2026
Verilog

arpita-kattul / Synchronous-FIFO-Verilog

Star

Synchronous FIFO design and verification using Verilog

fpga verification verilog vivado hdl digital-design rtl-design hardware-design synchronous-fifo

Updated Aug 10, 2026
Verilog

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